1. Field of the Invention
The invention relates to testing of semiconductor devices, and more particularly to an improved method for estimating overall quiescent currents in integrated circuits to facilitate the establishment of realistic test limits.
2. Description of the Related Art
Integrated circuits have become essential components of many consumer and commercial electronic product produced today, often replacing discrete components and enhancing functionality. The semiconductor processing technologies that produce these integrated circuits have advanced to the point where complete systems can often be reduced to a single integrated circuit. The evolution of the integrated circuit has not been uncomplicated, however. Continually shrinking device geometries, coupled with the high cost of operating semiconductor processing equipment, result in increased demands on integrated circuit suppliers to improve process yields and develop new test strategies.
Currently, complementary metal-oxide-semiconductor (CMOS) is the most popular technology for fabricating integrated circuits (ICs) due to its inherent low power consumption in high densities. CMOS circuits use complementary p-channel metal-oxide-semiconductor field-effect (PMOS) transistors and n-channel metal-oxide-semiconductor field-effect (NMOS) transistors to produce fully static designs that ideally consume no power except when switching states. In practice, however, CMOS circuits draw low leakage currents (also referred to as quiescent power supply current or IDDQ) in a static state. Quiescent current testing therefore provides a relatively simple and cost-effective test strategy for screening for physical defects.
The main goal of semiconductor test strategies is to screen out devices having functional or physical defects, while establishing test limits that do not reject good devices. Many test development strategies have evolved, and often combinations of these strategies are utilized to provide a high degree of fault coverage. Test development strategies include functional test wherein automatic test equipment (ATE) test programs are performed in which the circuit under test is stimulated with specified inputs while the outputs are monitored to determine if they correspond with simulated logic values. Structural tests are also utilized and rely on a model of logical circuit faults. These tests are often implemented using "boundary scan" or "full scan" circuitry in conjunction with structural test sets. Structural tests sometimes begin with functional logic simulations that have been fault graded and enhanced for higher fault coverage.
Another test development strategy, physical defect testing, involves creating specific tests designed to detect possible real physical defects that can occur in a circuit. Physical testing is useful for detecting defects that may not cause the device to fail functional or structural testing, but may lead to failure in the field. Defects in integrated circuits take many forms, some of which are test pattern sensitive. Gate oxide defects, drain to source current leaks (punch-through), and p-n junction current leaks (such as drain or source to diffusion current leaks) tend to be pattern sensitive, while resistive shorts to ground or the power supply voltage are usually pattern insensitive. In either case, quiescent current tests are a valuable tool in detecting faults.
Generally, the result of test development is an ATE test program or test "set" providing stimulus/response test "vectors" in the language of the ATE. The ATE test set causes the inputs of the device under test to be driven in a predetermined manner, while output pin voltages are compared to stored test values. The ATE test set is derived mainly from functional and structural test development logic simulations.
When testing quiescent current with a functional test set, the tester is generally halted at predetermined test steps suitable for quiescent current testing. Once halted (i.e., no switching is occurring) the power supply of the device under test is measured by the ATE and the resulting value is compared to predetermined reference values or test limits. Such quiescent current tests are effective in detecting many faults that would otherwise not be found by other test strategies.
For example, with most functional tests that measure voltage, faults must propagate to the output pins of the device under test for the ATE to differentiate between a good or bad device. Quiescent current tests differ in that current is sensed rather than voltage, providing a simple means to monitor the entire circuit or portions thereof for overcurrent conditions. The quiescent current measurements are typically accomplished via the tester's parametric unit.
Accurate quiescent current testing requires that the device under test be in a static DC condition, with any circuitry that draws current in the static DC condition being disabled or accounted for in the test limits. Preferably analog circuitry, input/output pads, and other circuity not conducive to quiescent current testing are provided with separate, dedicated power supply inputs, so that digital core circuitry can be tested separately.
Quiescent current varies with both the size of the integrated circuit as well as the minimum transistor channel length. Quiescent current dissipation is highest in transistors having a gate length that is at the minimum allowed by the process design rules. Such transistors account for the majority of transistors in a typical integrated circuit. Further, power supply voltages are continually being reduced in an effort to minimize power dissipation. However, reduced power supply voltages generally result in lower threshold voltages for transistors for a given fabrication process. Consequently, quiescent current increases as power supply voltages are lowered. These variations in quiescent current are not always adequately accounted for by existing estimation methods.
Quiescent current testing is currently performed by many semiconductor manufacturers, but no standardized method exists for selecting the quiescent current reference values or limits that determine whether a device passes or fails the test. Test limits are often quite loose and sometimes established on an arbitrary basis. One method involves simply estimating the number of transistors in a device and multiplying by a conversion factor. In another method, representative devices are sampled to arrive at an acceptable threshold. All of these prior methods for establishing quiescent current test limits suffer from inherent inaccuracies. If the quiescent current test limits are set too low, good devices may be rejected. If the quiescent current test limits are set too high, faulty devices may escape detection. In addition, a concern in establishing realistic quiescent current test limits is that high precision measurement of quiescent current requires a relatively long period of time. Thus, only a limited number of quiescent current test vectors are usually allowed. Currently, no satisfactory method exists for establishing quiescent current test limits.